1. Field of the Invention
This invention relates to hot carrier injection programmable flash EEPROM's, and more particularly to a floating gate memory cell operated in a low-energy programming mode permitting charge pump programming of at least 1024 memory cells.
2. Description of the Relevant Art
Flash EEPROM's are solid state memories and they store information in arrays of memory cells formed on substrates in rows and columns. The cells are programmed by injection of hot carriers into a floating gate structure within each cell. Currently, the internal operating voltages needed to program the cells are derived from a basic chip supply voltage, such as +5 VDC. The publication by Aritome et al. entitled "Reliability Issues of Flash Memory Cells" includes an interesting historical summary of EEPROM development, and is to be found in Proceedings of the IEEE, vol. 81, no. 5, page 776, published May 1993, and is incorporated here by reference.
These useful storage devices have succeeded in head-to-head competition with other solid state and rotating memories, especially among the laptop computer and hand-held devices. Yet despite this success, further market acceptance has been limited by a low data transfer rate during writing. One of the factors limiting the writing speed is the need for the internal power sources to provide a programming current which averages 300-500 .mu.A per cell. The on-chip power sources are typically unable to supply programming current for more than 8 or so cells at one time. Since a conventional cell is programmed in about 1 .mu.S, the resulting data transfer rate is too slow to handle a bandwidth which will allow the flash EEPROM to rapidly enlarge its market share.
Recently Kazerounian et al. in U.S. Pat. No. 5,042,009, issued Aug. 20, 1991 and in a publication entitled "A 5 Volt High Density Poly-Poly Erase Flash EPROM Cell," IEDM Tech. Dig., pp. 436-439, 1988, both incorporated herein by reference, disclosed a flash memory cell having a programming current of approximately 1 .mu.A. At such a current level it is possible to program simultaneously more than 8 cells using on-chip charge pumps to supply the necessary higher voltages. This cell points the way toward a flash EEPROM memory able to operate at higher data rates by writing many cells at one time.
The Kazerounian et al. reference teaches a split gate architecture requiring a separate doping area within the channel near the source region. The operation of the cells requires the application of specialized biasing schemes such as ramping the gate, high drain voltages, or pulsing the gate. Kazerounian et al limits the practical usefulness of the cell despite the benefits of the low programming current.
It would be desirable to obtain the benefits of a very low programming current while retaining the practical advantages of a conventional stacked gate cell architecture which relies upon conventional biasing on the gate and the drain. It would also be desirable to take advantage of a very low programming current to greatly increase the number of cells which can be programmed simultaneously, thereby increasing the writing speed. And finally, it would be desirable to provide a memory cell architecture in which the programming interval is significantly less than 1 mS.